Specifying Weak Memory Consistency with Temporal Logic

Modern multiprocessors only provide weak memory consistency that deviates from the traditional sequential consistency in many unintuitive ways: In essence, the read and write operations issued by one processor might be observed by other processors in a different order than executed by the issuing processor. It is therefore strongly recommended to formally verify multithreaded systems. To this end, it is necessary to offer unambiguous and complete descriptions of the used memory consistency models. Different formal methods have been used so far to specify the possible executions under particular weak memory consistency models. However, some of them cannot be directly used for verification by model checking. In this paper, we present a new way for specifying weak memory consistency models that is based on temporal logic. Using Linear Temporal Logic (LTL) to define weak memory systems, we can easily check properties of one and the same multithreaded program against several consistency models. This way, we can determine the weakest consistency guarantees required to ensure given specifications.